It is a well-known practice to employ memories as intermediate buffers between the components of a system for storing data written therein by the transmitting equipment at one speed, and read therefrom by destination equipment at another speed. Buffer random access memories have been developed which operate according to a First In First Out (FIFO) technique. In particular, copending Application Ser. No. 746,920 discloses a FIFO memory device that can be written and read within an exceptionally short period of time. This FIFO memory has a plurality of memory word locations having a common data-in bus for writing data directly into the memory locations, and a common data-out bus from which data can be directly read. A write address ring counter sequentially addresses each memory word location in response to input write commands. A read address ring counter operates similarly to sequentially read memory word locations in response to input read commands.
The write command of this FIFO memory generates a write clock pulse that comprises a first, negative-going transition and a second, positive-going transition. On the negative-going transition, the address is incremented to the next location. On the following positive-going transition, the address location to which the pointer had been incremented is written to the memory register. As will be explained in further detail below, a guard band or buffer time is generally inserted into the low side of the write cycle to avoid writing to a wrong address.
The FIFO memory of copending Application Ser. No. 746,920 writes on the high portion of an inverted write clock pulse, and increments the address pointer on the low portion of the next inverted pulse. The guard band is also on the low portion. The high portion and the low portion are generally of substantial length in order to allow the satisfactory completion of these operations. The interval between leading edges of write commands is equal to the combined length of the high and low portions.
The read cycle of this FIFO is substantially shorter than its write cycle. The maximum frequency associated with data transmission through the FIFO, or F.sub.max, is the inverse of the longer of the minimum permissible read and write cycle, as the full FIFO can read in new data only as fast as prior data can be written out. Therefore, while the FIFO memory of the copending application represents a significant improvement in through-put time, this time can be further reduced if the minimum permissible read and write cycles are made to be more nearly the same.